Embodiments described herein relate generally to a buffer module, and, in particular, to methods and apparatus related to a shared memory buffer for variable-sized cells.
Known low latency shared memory buffers can be used in many types of applications. For example, low latency shared memory buffers can be used in relatively high throughput network switch applications and in parallel computing systems. These known shared memory buffers often use a cut-through approach where the shared memory buffer is configured to transmit a head end (e.g., initial bit values) of, for example, a cell before a tail end (e.g., trailing bit values) of the cell has been completely received at an input port of the shared memory buffer. These known shared memory buffers can be configured to process cells having fixed bit-wise widths and/or process segments that have bit-wise widths equal to a minimum bit-wise width of a cell. These known shared memory buffers, however, often process the cells with an undesirable level of administrative overhead and/or are not configured to process variable-sized cells in a desirable fashion.
Thus, a need exists for methods and apparatus for a shared memory buffer configured to process variable-sized cells.